Hard-to-Detect Fault Analysis in FinFET SRAMs

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 29; no. 6; pp. 1271 - 1284
• Main Authors: Cardoso Medeiros, Guilherme, Fieback, Moritz, Wu, Lizhou, Taouil, Mottaqiallah, Bolzani Poehls, Leticia Maria, Hamdioui, Said
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit faults; Fault analysis; Fault detection; Field effect transistors; fin field-effect transistor (FinFET); FinFETs; hard-to-detect (HTD) faults; Integrated circuit modeling; Manufacturing; Manufacturing defects; Random access memory; Semiconductor devices; Static random access memory; static random access memory (SRAM); Systematics; test solutions; testing; Transistors
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3071940

Manufacturing defects can cause hard-to-detect (HTD) faults in fin field-effect transistor (FinFET) static random access memories (SRAMs). Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This article presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.