An Embedded DRAM Technology for High-Performance NAND Flash Memories

• Published in: IEEE journal of solid-state circuits Vol. 47; no. 2; pp. 536 - 546
• Main Authors: Takashima, D., Noguchi, M., Shibata, N., Kanda, K., Sukegawa, H., Fujii, S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.2012; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Arrays; Ash; Bandwidth; bit error rate; cache; Capacitance; Circuit properties; data retention; Design. Technologies. Operation analysis. Testing; Dielectric, amorphous and glass solid devices; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; embedded DRAM; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Microprocessors; NAND flash memory; page buffer; Random access memory; refresh operation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; soft error; Performance evaluation; NAND flash memory; Cache memory; Bit error rate; Random access memory; Spurious capacity; Logic circuit; Soft error; Non volatile memory; page buffer; Bandwidth; Dynamic random access memory; Execution time; High performance; NAND circuit; cache; Buffer system; Mismatching; MOS capacitor; refresh operation; High voltage; Flash memory; Manufacturing process; data retention; Integrated circuit; embedded DRAM; Reliability; Planar technology
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2170779

An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm 2 /Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performances. A 32 KB DRAM buffer macro with 1.5 μm 2 cell has been fabricated with a 32 nm NAND flash memory process. Even with small 3 fF cell using a planar MOS capacitor, an enough ±100 mV cell signal has been obtained by introducing a technique to self-boost cell node up to 4 V using a merit of high-voltage NAND flash process, and two techniques to curtail parasitic bitline capacitance down to 60 fF at 128 wordlines per bitline. An undershoot problem of cell nodes due to unwanted plateline bounce is resolved by a two-step-rise/fall wordline scheme. Installation of dummy cell scheme to obtain a half of "1" data (not an average of "1" and "0" data) cuts out 32 KB macro size by 1.3% while suppressing mismatch to 3 mV at the grounded bitline precharge. The 32 KB test vehicle shows 90 ns random cycle time with 15 ns burst cycle time (66 Mb/s/pin). The measured characteristics of 2 × 10 -18 bit error rater (BER) by soft error and 10 ms data retention at 85 °C are enough for page buffer application in a NAND flash memory. The measured active current of 32 KB macro is 7 mA at 90 ns random cycle, but only 3.2 mA at practical use of 15 ns burst with 256B page access.