A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 29; no. 5; pp. 871 - 882
• Main Authors: Mahmoudi, Azad, Torkzadeh, Pooya, Dousti, Massoud
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: ADC-based receiver; Algorithms; Analog to digital conversion; Analog to digital converters; Analog-to-digital converter (ADC); Bit error rate; CMOS; Complexity; Decision feedback equalizers; decision-feedback equalizer (DFE); Delays; Digital to analog conversion; Digital to analog converters; embedded DFE; Embedding; Equalization; Power consumption; Power demand; Receivers; Signal processing; Signal resolution; successive approximation register (SAR); Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3056316

Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for complex, flexible, and robust signal processing algorithms in the digital domain, as well as easy implementation of advanced modulation schemes beyond binary PAM2. However, the power consumption of the ADC and ensuing digital equalization is a key issue for such receivers in high-speed applications. Embedding analog equalization inside the ADC architecture allows for both a lower ADC resolution and a reduced-complexity digital equalizer, resulting in a more power-efficient receiver. This article presents a 6-bit 1.5-GS/s time-interleaved successive approximation register (SAR) ADC with low-overhead two-tap embedded decision-feedback equalizer (DFE). A smart speculative DFE is proposed to reduce additional conversion cycles required for the equalization realization in the ADC. Moreover, DFE functions are efficiently embedded in the capacitive digital-to-analog converter (DAC) references. The prototype ADC with two-tap DFE is implemented in a 130-nm CMOS process and achieves a 5.24-bit peak effective number of bits and 0.59-pJ/conversion-step figure-of-merit (FOM) at a 1.5-GS/s sampling rate while consuming 34.1 mW and occupying a core area of 0.32 mm 2 . The effectiveness of the embedded DFE in timing margin improvement is verified for 1.5-Gb/s operation over high-loss FR4 channels at a bit error rate (BER) of 10 −9 .