Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area

In this brief an improved Dickson charge pump (DCP) topology exploiting a clock boosting is presented. An accurate while simple theoretical model for the dynamic behavior of the charge pump is carried out. Analytical comparison with the traditional DCP reveals that the proposed solution can achieve...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 66; no. 12; pp. 1977 - 1981
Main Authors Ballo, A., Grasso, A. D., Giustolisi, G., Palumbo, G.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Capacitance
Charge pumps
Circuits
Clock booster
Clocks
CMOS
Computer simulation
Current carriers
DC-DC converter
Dickson charge pump
Integrated circuit modeling
Mathematical models
Model accuracy
SC converter
Silicon
Steady-state
Topology
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Summary:In this brief an improved Dickson charge pump (DCP) topology exploiting a clock boosting is presented. An accurate while simple theoretical model for the dynamic behavior of the charge pump is carried out. Analytical comparison with the traditional DCP reveals that the proposed solution can achieve a rise time or area reduction between 10% and 60% at the cost of a slight circuit complexity. Finally, simulation results using a 65-nm CMOS technology show the accuracy of the analytical model as well as the advantages of the proposed solution.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2019.2898716