Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 48; no. 5; pp. 1199 - 1211
• Main Authors: Sadhu, Bodhisatwa, Sturm, Martin, Sadler, Brian M., Harjani, Ramesh
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.05.2013; Institute of Electrical and Electronics Engineers
• Subjects: analog integrated circuits; Analytical models; Applied sciences; Bandwidth; Capacitors; channel bank filters; Circuit properties; Clocks; cognitive radio; demodulation; Design. Technologies. Operation analysis. Testing; discrete cosine transforms; Discrete Fourier transforms; Dynamic range; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Engines; Exact sciences and technology; fast Fourier transforms; FET integrated circuits; filtering; FIR filters; Frequency filters; Hardware; Input-output equipment; integrated circuit modeling; integrated circuit noise; Integrated circuits; linear circuits; mixed analog digital integrated circuits; modulation; MOS integrated circuits; multiple signal classification; multiplying circuits; OFDM; passive circuits; passive filters; phase shifters; Radio frequency; radio spectrum management; radio-frequency integrated circuits; RF signals; sampled data circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; signal analysis; signal detection; signal sampling; signal to noise ratio; software defined radio; software radio; spectral analysis; summing circuits; switched capacitor; switched circuits; transforms; Transistors; very high speed integrated circuits; fast Fourier transforms; very high speed integrated circuits; Fourier transformation; Fast Fourier transformation; OFDM; modulation; RF signals; Discrete Fourier transformation; transforms; spectral analysis; passive filters; mixed analog digital integrated circuits; Wide band; Nominal value; filtering; Dynamic response; integrated circuit noise; software defined radio; radio-frequency integrated circuits; phase shifters; Field effect transistor; switched capacitor; Finite impulse response filter; Software; signal to noise ratio; Signal to noise and distortion ratio; Analogue integrated circuits; Demodulation; integrated circuit modeling; multiplying circuits; switched circuits; Modeling; Implementation; linear circuits; Analytical models; FIR filters; cognitive radio; multiple signal classification; software radio; User interface; Complementary MOS technology; FET integrated circuits; signal sampling; Discrete cosine transforms; MOS integrated circuits; summing circuits; channel bank filters; Non ideality; radio spectrum management; signal analysis; signal detection; discrete Fourier transforms; analog integrated circuits; passive circuits; Integrated circuit; Analytical method; sampled data circuits; Low-power electronics
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2250457

This work describes the design of a 16 point analog domain FFT using a Charge Re-use Analog Fourier Transform (CRAFT) engine. The circuit relies on charge re-use to achieve 47 dB average output SNDR on an instantaneous input bandwidth of 5 GHz, and consumes only 3.8 mW (12.2 pJ/conv.). The CRAFT engine is used as a wide-band, low power RF front-end channelizer for software defined radio (SDR) applications. The paper also discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation. These techniques enable this implementation to achieve a large dynamic range even at high speeds.