Simplified Model of the Effect of Source/Drain Doping Gradient on Capacitance and Resistance in a Double-Gate Metal--Oxide--Semiconductor Field-Effect Transistor

Simplified models of capacitance and resistance in the external region are presented and the mobility enhancement effect is verified for extremely scaled and undoped double-gate metal--oxide--semiconductor field-effect transistors (MOSFETs) with the raised source/drain and self-aligned silicide stru...

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Bibliographic Details
Published inJapanese Journal of Applied Physics Vol. 50; no. 6; pp. 06GF16 - 06GF16-5
Main Authors Moon, Dae-hyun, Song, Jae-Joon, Kim, Ohyun
Format Journal Article
LanguageEnglish
Published The Japan Society of Applied Physics 01.06.2011
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Summary:Simplified models of capacitance and resistance in the external region are presented and the mobility enhancement effect is verified for extremely scaled and undoped double-gate metal--oxide--semiconductor field-effect transistors (MOSFETs) with the raised source/drain and self-aligned silicide structure and different source/drain doping gradients. The accuracy and universality of these models were confirmed using a two-dimensional simulator. Results indicated that a 3 nm increment of the source/drain lateral doping straggle can reduce the intrinsic delay by about 30% and the leakage current by about 95%.
Bibliography:(a) 3D schematic of the simulated double-gate FinFET structure and (b) 2D schematic cross-sectional view from the cut-line A--A$'$ of the 3D figure. S/D doping gradient profiles close to Si/SiO 2 interfaces with lateral straggle from 1 to 4 nm. The effective channel length and external length change are shown schematically. Process flow for the fabrication of raised S/D and SALICIDE structure with various doping gradient devices. Schematics of (a) the outer fringe capacitance in the strong inversion region and (b) dividing all regions into two regions for simplified modeling. (a) Total capacitance and total resistance versus S/D lateral straggle. (b) Carrier mobility in external region versus S/D lateral straggle. Lines: model values; Symbols: simulation results. Total capacitance at $\sigma = 1$ and 4 nm as a function of dielectric constant. Lines: model values; Symbols: simulation results using SiO 2 , Si 3 N 4 , and HfO 2 as the gate dielectric. Total capacitance and total resistance versus S/D lateral straggle with year of production from 2015 to 2017. Lines: model values; Symbols: simulation results. Intrinsic delay and leakage current versus S/D lateral straggle. Lines: model values, Symbols: simulation results; Histogram: off current ($V_{\text{gs}} = 0.0$ V, $V_{\text{ds}} = V_{\text{dd}} = 0.85$ V) from the simulator.
ISSN:0021-4922
1347-4065
DOI:10.1143/JJAP.50.06GF16