Implementation of Dynamic Matrix Control on Field Programmable Gate Array
High performance computer is often required by model predictive control (MPC) systems due to the heavy online computation burden. To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array (FPGA) system is studi...
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Published in | Shanghai jiao tong da xue xue bao Vol. 16; no. 4; pp. 441 - 446 |
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Main Author | |
Format | Journal Article |
Language | English |
Published |
Heidelberg
Shanghai Jiaotong University Press
01.08.2011
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Subjects | |
Online Access | Get full text |
ISSN | 1007-1172 1995-8188 |
DOI | 10.1007/s12204-010-1086-z |
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Summary: | High performance computer is often required by model predictive control (MPC) systems due to the heavy online computation burden. To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array (FPGA) system is studied. For the dynamic matrix control (DMC) algorithm, the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA's embedded system. The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA. |
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Bibliography: | LAN Jian , LI De-wei, YANG Nan, XI Yu-geng (Department of Automation, Shanghai Jiaotong University; Key Laboratory of System Control and Information Processing Ministry of Education, Shanghai 200240, China) High performance computer is often required by model predictive control (MPC) systems due to the heavy online computation burden. To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array (FPGA) system is studied. For the dynamic matrix control (DMC) algorithm, the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA's embedded system. The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA. 31-1943/U model predictive control (MPC), dynamic matrix control (DMC), quadratic programming (QP), active set, programmable logic device, field programmable gate array (FPGA) ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 ObjectType-Article-2 ObjectType-Feature-1 |
ISSN: | 1007-1172 1995-8188 |
DOI: | 10.1007/s12204-010-1086-z |