FlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic

• Published in: IEEE solid-state circuits letters Vol. 6; p. 1
• Main Authors: Stanger, Inbal, Shavit, Netanel, Taco, Ramiro, Lanuzza, Marco, Yavits, Leonid, Levi, Itamar, Fish, Alexander
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arithmetic; Arithmetic and logic units; Clocks; CMOS; Configurable computing; Delays; Design optimization; DML; Dual Mode Logic; Dynamic; Energy consumption; Hardware; Logic gates; Mixed-mode; Optimization; Performance enhancement; Pipeline; Pipelines; Static
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2023.3259102

Dual Mode Logic (DML) enables flexible energy-delay optimization. By setting the design elements in static or dynamic mode, it is possible to significantly improve performance at the cost of a limited increase in energy consumption, and vice versa. In this work, for the first time, we design, fabricate in a commercial 16nm FinFET process, and evaluate in silicon FlexDML, an adaptively configurable arithmetic unit. FlexDML comprises several DMLBricks, 2×2 and 4×4 DML-based multiplier units, as well as DML-based shifters and adders. FlexDML is capable of performing several arithmetic operations with flexible wordlength, such as N×N-bit, two (N/2)×N-bit or N×(N/2)-bit, four (N/2)×(N/2)-bit and so on multiplications, as well as shifts and inner product calculations. All DMLBricks can be operational at the same time, increasing the hardware utilization to the level unattainable in typical designs that support variable wordlength. FlexDML is the first to support a pipeline multimode, where the DML mode is set separately for each pipeline stage, thus enabling more flexible energy-delay optimization. FlexDML achieves up to 41% performance improvement in dynamic mode, and power savings of about 23% in static mode, compared to CMOS implementation.