A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 58; no. 4; pp. 1062 - 1073
• Main Authors: Nishi, Yoshinori, Poulton, John W., Turner, Walker J., Chen, Xi, Song, Sanquan, Zimmer, Brian, Tell, Stephen G., Nedovic, Nikola, Wilson, John M., Dally, William J., Gray, C. Thomas
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bidirectional control; chip on wafer on substrate (CoWoS); Chip-to-chip; chiplet and interposer; Clocks; CMOS; Delays; die-to-die; Integrated circuit interconnections; integrated fan-out (InFO); Inverters; ISR; Optical communication; Optical signal processing; Optical switches; Receivers; short-reach; Silicon; simultaneous bi-directional; simultaneous bi-directional signaling (SBD); ultra-short-reach (USR); very-short-reach (VSR); Wire
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3232024

This article presents a clock-forwarded, inverter-based short-reach simultaneous bi-directional (ISR-SBD) physical layer (PHY) targeted for die-to-die communication over silicon interposers or similar high-density interconnect. Short-reach links of this type are increasingly important to support larger systems built with chiplets and multiple die and to facilitate the shift to medium- and long-range optical communication based on silicon photonics. This project explores the advantages of simultaneous bi-directional signaling (SBD) over other bandwidth-doubling techniques (e.g., PAM4). Fabricated in a 5-nm standard CMOS process, the ISR-SBD PHY demonstrates 50.4 Gb/s/wire (25.2 Gb/s each direction) and 0.297 pJ/bit on a 750-mV supply over a 1.2-mm on- chip channel.