A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier

This article presents a process, voltage, and temperature (PVT)-robust capacitively degenerated dynamic amplifier as the residue amplifier of the low-power pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier achieves a voltage gain of 1...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 58; no. 4; pp. 961 - 971
Main Authors Yoon, Hyunchul, Lee, Changuk, Kim, Taewoong, Kwon, Yigi, Chae, Youngcheol
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:This article presents a process, voltage, and temperature (PVT)-robust capacitively degenerated dynamic amplifier as the residue amplifier of the low-power pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier achieves a voltage gain of 16 with a two-stage configuration and high linearity over a wide temperature range with an on-chip timing generator. This work solves problems related to the low voltage gain and high temperature-sensitivity of the capacitively degenerated dynamic amplifier, while retaining the advantages of high linearity, wide output swing, and high energy efficiency. The prototype ADC is implemented in a 65-nm CMOS process and achieves 65-dB signal-to-noise-and-distortion ratio (SNDR) and 79.8-dB spurious free dynamic range (SFDR) at a sampling rate of 50 MS/s, while consuming only 0.46 mW. The power overhead of the timing generator is only 10% of the overall power consumption. It shows only 0.7-dB and 1.86-dB SNDR variations at 0.8-1.0-V supply variation and 0 °C-100 °C temperature variation, respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2023.3235521