A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces

• Published in: IEEE journal of solid-state circuits Vol. 58; no. 10; pp. 1 - 12
• Main Authors: Huang, Jia-Sheng, Kuo, Shih-Che, Chen, Chia-Hung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Analog-digital conversion; Analog-to-digital converters (ADC); Circuits; decimation filter; delta sigma (<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> Delta \Sigma )</tex-math> </inline-formula>; delta sigma modulator; Digital filters; Energy dissipation; high-resolution; incremental; low latency; Measurement; measurement and instrumentation; Modulation; Modulators; Multi-stage noise shaping; Multiplexing; multistage noise-shaping (MASH); multistep; Noise levels; Quantization (signal); sensor interface; Sensors; Sigma-delta modulation; switched-capacitor (SC) circuits; System on chip; Timing

Incremental analog-to-digital converters (IADCs), by adding a simultaneous reset in analog modulators and digital filters, are Nyquist-rate ADCs which use noise-shaping to convert a finite number of analog samples into a single digital word. They retain most advantages of the delta sigma (<inline...