A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces

• Published in: IEEE journal of solid-state circuits Vol. 58; no. 10; pp. 1 - 12
• Main Authors: Huang, Jia-Sheng, Kuo, Shih-Che, Chen, Chia-Hung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Analog-digital conversion; Analog-to-digital converters (ADC); Circuits; decimation filter; delta sigma (<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> Delta \Sigma )</tex-math> </inline-formula>; delta sigma modulator; Digital filters; Energy dissipation; high-resolution; incremental; low latency; Measurement; measurement and instrumentation; Modulation; Modulators; Multi-stage noise shaping; Multiplexing; multistage noise-shaping (MASH); multistep; Noise levels; Quantization (signal); sensor interface; Sensors; Sigma-delta modulation; switched-capacitor (SC) circuits; System on chip; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2023.3288198

Incremental analog-to-digital converters (IADCs), by adding a simultaneous reset in analog modulators and digital filters, are Nyquist-rate ADCs which use noise-shaping to convert a finite number of analog samples into a single digital word. They retain most advantages of the delta sigma (<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma )</tex-math> </inline-formula> ADCs, and are much easier to be multiplexed with shorter latency and simpler digital filters. Integrated sensor fusion system-on-chips (SoCs) require a high-accuracy low-latency analog-to-digital converter (ADC) to interface a wide input range signal and multiplex among multiple sensor channels. To fulfill these demands at the same time, a multistage multistep incremental ADC is proposed. A third-order multistage IADC, implemented by cascading a second-order IADC (IADC2) and a first-order IADC (IADC1), performs the coarse quantization in the first step. When the coarse quantization is finished, the residue is also accumulated at the last integrator's output and is ready for fine quantization. The circuit is reused and reconfigured as a second IADC in the second step. Prototyped in 180 nm technology and power supplied at 1.8 V, the proposed work can achieve 20 kHz signal bandwidth with 358.4 <inline-formula> <tex-math notation="LaTeX">\mu </tex-math> </inline-formula>W power dissipation. The measured performance of the prototype is 91 dB dynamic range (DR), 89.1 dB signal-to-noise-and-distortion (SNDR), and 107.5 dB spurious-free DR (SFDR). The measured SNDR/DR achieves Schreier figure-of-merit (FoM) of 166.6/168.5 dB.