Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

• Published in: IEEE journal of solid-state circuits Vol. 58; no. 7; pp. 2098 - 2108
• Main Authors: Yokoyama, Yoshisato, Nii, Koji, Ishii, Yuichiro, Tanaka, Shinji, Kobayashi, Kazutoshi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 28 nm; 40 nm; 7 nm; <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V min; Circuit design; Clocks; Design; disturbance; dual port (DP); dynamic power; Electronics packaging; Logic gates; MOS devices; Power consumption; Pulse duration; Random access memory; row access; Static random access memory; static random access memory (SRAM); Threshold voltage; Timing; wordline (WL) pulse
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3229828

An effective design is proposed to reduce dynamic power consumption for a common clock synchronous two-read/ write (2RW) dual-port (DP) 8T static random access memory (SRAM). A self-adjusting wordline (WL) pulse timing control circuit is newly introduced for read/write operations. Row address inputs of ports A and B are compared in each cycle to detect the same row access or not. In the same row access from both ports, the disturbance should happen, which is an inherent mode of 2RW DP 8T SRAM. Then, the WL pulsewidth is extended to prevent the disturbance, while maintaining sufficient read/write margins. In the different row access, where there is no disturbance, the WL pulsewidth is shortened to reduce excessive bitline (BL) discharge power. Test chips are designed and fabricated to implement the proposed 2RW DP SRAM macros on 40-, 28-, and 7-nm Fin-FET technologies. Measured data show that read and write powers are reduced, respectively, by 6%-13% and 13%-28% with the proposed circuits. No speed degradation is found compared to conventional designs. Area overheads are found to be less than 1%.