Assessment and Comparison of Measurement-Based Large-Signal FET Models for GaN HEMTs

• Published in: IEEE transactions on microwave theory and techniques Vol. 72; no. 5; pp. 2692 - 2703
• Main Authors: Perez Martinez, Rafael, Iwamoto, Masaya, Xu, Jianjun, Gillease, Chad, Cochran, Steven, Culver, Morgan, Cognata, Alex, Wagner, Natalie S., Pahl, Philipp, Chowdhury, Srabanti
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Benchmarks; Capacitance; Data models; Device modeling; Field effect transistors; Gallium nitride; gallium nitride (GaN) high-electron-mobility transistor (HEMT); Gallium nitrides; HEMTs; High electron mobility transistors; Integrated circuit modeling; linearity; Logic gates; Mathematical models; Modelling; MODFETs; Network analysers; Neural networks; Parameters; Semiconductor devices; thermal effects; trapping effects
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2023.3349172

An assessment in the context of gallium nitride (GaN) high-electron-mobility transistor (HEMT) modeling of three measurement-based large-signal FET models natively implemented in the Keysight PathWave Advanced Design System (ADS) is done by extracting, validating, and benchmarking the three models. The strengths and limitations of using table and neural network-based approaches for modeling <inline-formula> <tex-math notation="LaTeX">I </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">V </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">Q </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">V </tex-math></inline-formula> relationships are investigated. This is accomplished by characterizing a 150-nm gate length GaN-on-SiC HEMT with a gate width of <inline-formula> <tex-math notation="LaTeX">8\,\, {}\times {}50~\mu \text{m} </tex-math></inline-formula>. The same dataset is used to extract the three FET models, based on dc-IV, S-parameters, and nonlinear vector network analyzer (NVNA) data, which fall within the operational range of the device. The models are then validated at the device level using small-signal data for different operating conditions, temperatures, and geometries as well as large-signal load-pull data from X-parameters. A circuit-level validation is also performed to showcase the ability of the three models to predict circuit-level performance. By benchmarking the three models, we demonstrate the strengths and limitations of neural network technology to account for geometry scaling and thermal/trapping effects of GaN HEMTs.