A low substrate leakage junction isolated p-n-p-n crosspoint array

• Published in: IEEE journal of solid-state circuits Vol. 13; no. 2; pp. 210 - 218
• Main Authors: Shackle, P.W., Hartman, A.R., Adrian, J.M., Pritchett, R.L.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.1978
• Subjects: Charge carrier processes; Computational modeling; Computer simulation; Doping profiles; Gold; P-n junctions; Solid state circuits; Switching systems; Telephony; Thyristors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1978.1051021

A 4/spl times/8 p-n-p-n crosspoint array for telephone switching networks is described which uses a junction isolated structure to achieve low substrate leakage. The structure uses collector diffusion isolation in conjunction with gold doping to reduce the substrate leakage to less than one part in 10/SUP 5/. This low substrate leakage is shown to be a necessary feature when a solid-state crosspoint is used in a large switching system. The paper includes computer simulated curves of electron and hole density through the doping profile illustrating how the gold doping affects the substrate leakage. The array consists of a 4/spl times/8 matrix of silicon controlled rectifiers each with a gate diode and gate shunting resistor. The layout of the chip, its design constraints and design calculations are described. The chip is fabricated with nitride passivated beam-lead technology and may be packaged in either a hybrid integrated circuit or an 18-lead DIP. The SCR's have forward and reverse leakages of 10 nA at 30 V, a holding current of 1.1 mA, and a gate trigger current of 0.6 mA. With an on-state resistance which typically lies within 9/spl plusmn/1 /spl Omega/ for any matrix path and an off-state capacitance of 1 pF, the chip is suitable for application in the full range of telephone switching systems.