High Throughput and Hardware Efficient Hybrid LDPC Decoder Using Bit-Serial Stochastic Updating

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 70; no. 9; pp. 1 - 12
• Main Authors: Hu, Shuai, Han, Kaining, Zhu, Yubin, Shen, Guodong, Wang, Fujie, Hu, Jianhao
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Codes; Conversion; Decoders; Decoding; EPON; Error correcting codes; fully correlated stochastic; Hardware; IEEE 802.3 Standard; Iterative decoding; LDPC code; min-sum algorithm; Nodes; Performance degradation; Performance enhancement; probability tracer; Stochastic processes; Throughput
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2023.3280201

Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic decoding to achieve high performance and low complexity simultaneously. However, lossy and inefficient stochastic-to-binary (S2B) conversion brings extra performance degradation and decoding latency. In this paper, a bit-serial stochastic updating based hybrid decoding (BSSU-HD) is proposed, which employs fully correlated stochastic (FCS) check nodes (CNs) and probability tracers assisted variable nodes (VNs) to accomplish accurate and efficient S2B conversion. Two strategies, including random source selection and tracing speed switching, are proposed to further improve performance and convergence. A BSSU LDPC decoder for IEEE 802.3an is designed in a 65-nm CMOS process, which occupies 4.6 mm<inline-formula> <tex-math notation="LaTeX">^2</tex-math> </inline-formula> silicon area and achieves a throughput of 200.8 Gb/s at <inline-formula> <tex-math notation="LaTeX">E_b/N_0 = 4.4</tex-math> </inline-formula> dB with 500 MHz clock frequency from a 1.2 V supply voltage. The power and energy efficiency are 2.933 W and 14.61 pJ/bit, respectively. To the best of our known, it achieves the best decoding performance, the highest throughput and hardware efficiency among state-of-the-art IEEE 802.3an LDPC decoders. We also verify that the BSSU-HD can achieve better performance for multi-rate 5th generation (5G) New Ratio (NR) LDPC codes than conventional algorithm, which greatly extends the application of the stochastic decoding.