Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

• Published in: Electronics letters Vol. 42; no. 20; pp. 1151 - 1152
• Main Authors: DESCAMPS, P, BARBIER-PETOT, C, BIARD, C, BARDY, S
• Format: Journal Article
• Language: English
• Published: London Institution of Electrical Engineers 28.09.2006
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Parasitic behavior; Performance evaluation; High performance; Compact design; Electrical model; Silicon on insulator technology; Guard ring; Model matching; p type semiconductor; Complementary MOS technology; Integrated circuit; Testing equipment; Radiofrequency integrated circuits; CMOS integrated circuits; Comparative study; Electrical characteristic
• ISSN: 0013-5194; 1350-911X
• DOI: 10.1049/el:20061830

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50 x 50 um cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate.