Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design tech...

Full description

Saved in:
Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 69; no. 6; pp. 2249 - 2262
Main Authors Tang, Xiyuan, Liu, Jiaxin, Shen, Yi, Li, Shaolan, Shen, Linxiao, Sanyal, Arindam, Ragab, Kareem, Sun, Nan
Format Journal Article
LanguageEnglish
Published New York IEEE 01.06.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Analog circuits
Analog to digital converters
Analog-digital conversion
Analog-to-digital converter (ADC)
Bandwidth
Capacitors
Circuit design
Clocks
Design
Digital to analog converters
energy efficiency
Error analysis
Jitter
low power
Registers
successive approximation register (SAR)
Voltage
Online AccessGet full text

Cover

More Information
Summary:This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3166792