OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology

• Published in: IEEE transactions on parallel and distributed systems Vol. 28; no. 5; pp. 1390 - 1402
• Main Authors: Waidyasooriya, Hasitha Muthumala, Takei, Yasuhiro, Tatsumi, Shunsuke, Hariyama, Masanori
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Bandwidth; C (programming language); Central processing units; Computation; Computational modeling; Computer architecture; CPUs; Debugging; FDTD; Field programmable gate arrays; Graphics processing units; high performance computing; Kernel; Multicore processing; OpenCL for FPGA; Optimization; Programming languages; stencil computation
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2016.2614981

Stencil computation is widely used in scientific computations and many accelerators based on multicore CPUs and GPUs have been proposed. Stencil computation has a small operational intensity so that a large external memory bandwidth is usually required for high performance. FPGAs have the potential to solve this problem by utilizing large internal memory efficiently. However, a very large design, testing and debugging time is required to implement an FPGA architecture successfully. To solve this problem, we propose an FPGA-platform using C-like programming language called open computing language (OpenCL). We also propose an optimization methodology to find the optimal architecture for a given application using the proposed FPFA-platform. According to the experimental results, we achieved 119 - 237 Gflop/s of processing power and higher processing speed compared to conventional GPU and multicore CPU implementations.