FPGA-Type Configurable Coprocessor Implementation Scheme of Recurrent Neural Network for Solving Time-Varying QP Problems

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 69; no. 6; pp. 2502 - 2515
• Main Authors: Zhang, Zhijun, He, Haotian, Deng, Xianzhi, Xie, Jilong, Luo, Yamei
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: accelerated coprocessor; Automation; Coprocessors; Delays; Digital computers; Field programmable gate arrays; Iterative methods; Lookup tables; Neural networks; Quadratic programming; Random access memory; recurrent neural network; Recurrent neural networks; Reduced instruction set computing; time-varying problem; Time-varying systems
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2022.3153560

Many scientific and engineering applications can be formulated as a time-varying quadratic programming (TVQP) problem, and effectively solving it is an attractive issue. In order to solve the TVQP problem with multiple constraints effectively, a penalty-strategy varying-gain recurrent neural network (PSVG-RNN) combined is proposed, and is implemented with a field-programmable gate array (FPGA) and packaged into a configurable coprocessor. Comparative experiments verify that the coprocessor has at least an order of magnitude better performance than traditional Euler iterative method and Ode45 method embedded in Matlab implemented in digital computer. Experimental results show that the proposed PSVG-RNN only needs 382 lookup table random-access memories (LUTRAMs), 25583 lookup tables (LUTs) and 9549 flip-flops (FFs) of the Xilinx ZCU102 evaluation board.