n-p-n Array Yield Improvement in a 0.18-μm Deep Trench SiGe BiCMOS Process

• Published in: IEEE transactions on electron devices Vol. 59; no. 3; pp. 590 - 595
• Main Authors: Dong Gan, Chun Hu, Parker, G. E., Pao, H. H., Jolly, G.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2012; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Arrays; Bipolar CMOS (BiCMOS); collector leakage current; deep trench (DT); Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Leakage current; Oxidation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Silicon germanium; silicon germanium (SiGe); Stress; tensile stress; Transistors; Semiconductor alloys; Trench technology; Ge-Si alloys; Transmitter; silicon germanium (SiGe); Dislocation; BiCMOS technology; deep trench (DT); collector leakage current; Tensile stress; Complementary MOS technology; Collector; Germanium; Leakage current; Oxidation; Silicon; Bipolar CMOS (BiCMOS); Cost lowering; Base collector junction; Binary alloy
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2179806

The deep trench (DT) process module shows a strong impact on SiGe BiCMOS n-p-n array yield. DT liner oxidation introduces large tensile stress at the top of DT corners and in the vicinity of intrinsic SiGe base/collector regions. The increased tensile stress can result in dislocations in silicon. By replacing the 100-nm wet oxidation DT liner with a TEOS deposition liner, n-p-n array collector-emitter leakage yield can be improved from 64% to 94% in the investigated 0.18-μm DT SiGe BiCMOS process, comparable to the yield of a non-DT low-cost SiGe BiCMOS process.