3-9-GHz CMOS LNA Using Body Floating and Self-Bias Technique for Sub-6-GHz 5G Communications

• Published in: IEEE microwave and wireless components letters Vol. 31; no. 6; pp. 608 - 611
• Main Authors: Chang, Jin-Fa, Lin, Yo-Sheng
• Format: Journal Article
• Language: English
• Published: IEEE 01.06.2021
• Subjects: Body floating resistor; CMOS; Immune system; Inductors; low noise amplifier (LNA); low power (LP); Low-noise amplifiers; Noise measurement; self-body bias; Substrates; Transistors; wideband; Wireless communication
• ISSN: 1531-1309; 1558-1764
• DOI: 10.1109/LMWC.2021.3075279

We propose the body floating and self-bias technique, in which the body of the transistor is connected to its drain through a resistance (13.6 <inline-formula> <tex-math notation="LaTeX">\text{k}\Omega </tex-math></inline-formula> in this work). A low-power 3-9-GHz CMOS low-noise amplifier (LNA) using the technique for sub-6-GHz 5G systems is reported. An enhancement in <inline-formula> <tex-math notation="LaTeX">S_{21} </tex-math></inline-formula> and noise figure (NF) of the LNA is achieved due to the forward body-to-source bias (<inline-formula> <tex-math notation="LaTeX">V_{\mathrm {BS}} </tex-math></inline-formula>) (i.e., small threshold voltage <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {th}} </tex-math></inline-formula>) and the transistors being free from the substrate leakage. Low power is achieved since low supply voltage (<inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} </tex-math></inline-formula>) of 1 or 0.8 V is applicable because of small <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {th}} </tex-math></inline-formula>. At <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} </tex-math></inline-formula> of 1 V, the LNA consumes 3.3 mW and achieves prominent <inline-formula> <tex-math notation="LaTeX">S_{11} </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">- 10.1\,\,\text {to}\,\,-41.6 </tex-math></inline-formula> dB, <inline-formula> <tex-math notation="LaTeX">S_{21} </tex-math></inline-formula> of 10.7 dB, and NF of 2.89 dB for 3-9 GHz. At <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} </tex-math></inline-formula> of 0.8 V, the LNA consumes 1.36 mW and achieves <inline-formula> <tex-math notation="LaTeX">S_{11} </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">- 10\,\,\text {to}\,\,-45.8 </tex-math></inline-formula> dB, <inline-formula> <tex-math notation="LaTeX">S_{21} </tex-math></inline-formula> of 9.4 dB, and NF of 3.46 dB. To the authors' knowledge, both are one of the lowest power values ever reported for CMOS LNAs with bandwidth greater than 6 GHz and NF under 3.5 dB.