Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory

• Published in: IEEE transactions on emerging topics in computing Vol. 9; no. 2; pp. 745 - 758
• Main Authors: Liu, Peng, You, Zhiqiang, Wu, Jigang, Elimu, Michael, Wang, Weizheng, Cai, Shuo, Han, Yinhe
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Circuit faults; Circuits; CMOL; CMOS; Computer architecture; Computer memory; Defects; Discrete Fourier transforms; memristor; Memristors; Nanowires; Non-volatile memory; Power consumption; Random access memory; Resistance; RRAM; Testability; Testing; Testing time
• ISSN: 2168-6750; 2168-6750
• DOI: 10.1109/TETC.2020.2982830

CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately <inline-formula><tex-math notation="LaTeX">5n/4\times</tex-math> <mml:math><mml:mrow><mml:mn>5</mml:mn><mml:mi>n</mml:mi><mml:mo>/</mml:mo><mml:mn>4</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq1-2982830.gif"/> </inline-formula> and <inline-formula><tex-math notation="LaTeX">n\times</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq2-2982830.gif"/> </inline-formula>, respectively, where <inline-formula><tex-math notation="LaTeX">n</tex-math> <mml:math><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="liu-ieq3-2982830.gif"/> </inline-formula> is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.