On a Highly Efficient RDO-Based Mode Decision Pipeline Design for AVS

• Published in: IEEE transactions on multimedia Vol. 15; no. 8; pp. 1815 - 1829
• Main Authors: Zhu, Chuang, Jia, Huizhu, Zhang, Shanghang, Huang, Xiaofeng, Xie, Xiaodong, Gao, Wen
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Artificial intelligence; AVS; Coding, codes; Computer architecture; Computer science; control theory; systems; Electronics; Encoding; Exact sciences and technology; Hardware; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); mode decision; Pattern recognition. Digital image processing. Computational geometry; pipeline; Pipeline processing; Pipelines; RDO; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Telecommunications and information theory; Throughput; Video coding; Hardware description languages; Pipeline processor; Architectural design; Rate distortion theory; Logic gate; Processing time; Real time; Computational complexity; Modeling; Adaptive method; Optimization; pipeline; Image coding; Efficiency; Complementary MOS technology; VHDL language; Transmission rate; throughput; RDO; mode decision; AVS; Signal to noise ratio
• ISSN: 1520-9210; 1941-0077
• DOI: 10.1109/TMM.2013.2280446

Rate distortion optimization (RDO) is the best known mode decision method, while the high implementation complexity limits its applications and almost no real-time hardware encoder is truly full-featured RDO based. In this paper, first, a full-featured RDO-based mode decision (MD) algorithm is presented, which makes more modes enter RDO process. Second, the throughput of RDO-based MD pipeline is thoroughly analyzed and modeled. Third, a highly efficient adaptive block-level pipelining architecture of RDO-based MD for AVS video encoder is proposed which can achieve the highest throughput to alleviate the RDO burden. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18- μm CMOS technology with 232 K logic gates and 85 Kb SRAMs. The implementation results validate our architectural design and the proposed architecture can support real time processing of 1080P@30 fps. The coding efficiency of our adopted method far outperforms (0.57 dB PSNR gain in average) the traditional low-complexity MD (LCMD) methods and the throughput of our designed pipeline is increased by 11.3%, 19% and 17% for I, P and B frames, respectively, compared with the existed RDO-based architecture.