An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier

• Published in: IEEE journal of solid-state circuits Vol. 55; no. 4; pp. 1011 - 1022
• Main Authors: Tang, Xiyuan, Shen, Linxiao, Kasap, Begum, Yang, Xiangxing, Shi, Wei, Mukherjee, Abhishek, Pan, David Z., Sun, Nan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifier design; Amplifiers; Common-mode rejection; dynamic biasing; dynamic comparator; Energy efficiency; energy efficient; Inverters; latch-type comparator; low-noise; Noise reduction; Power efficiency; strong-arm (SA)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2960485

This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting <inline-formula> <tex-math notation="LaTeX">g_{m}/I_{D} </tex-math></inline-formula> and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46-<inline-formula> <tex-math notation="LaTeX">\mu \text{V} </tex-math></inline-formula> input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.