SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 62; no. 6; pp. 1538 - 1545
• Main Authors: Younghwi Yang, Juhyun Park, Seung Chul Song, Wang, Joseph, Yeap, Geoffrey, Seong-Ook Jung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Back gate; CD recordable; Circuit stability; extremely thin silicon-on-insulator (ETSOI); Inverters; Logic gates; MOS devices; Random access memory; read-assist circuit; SRAM cells; static random-access memory (SRAM); Transistors; write-assist circuit
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2015.2416814

As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the attractive candidates to reduce this mismatch, and it offers an independent back-gate control using a thin buried oxide. The implementation of back-gate control has recently attracted much interest to improve the read stability and write ability. In this paper, we propose a selective cell current (ICELL) boosting scheme (SIB) and an asymmetric back-gate control write-assist (ABC-WA) circuit. SIB enhances the read performance by selectively boosting ICELL of the SRAM cells. ABC-WA enhances the write ability by forward biasing the NMOSs at one side, which improves the write ability with reduction in the dynamic power overhead and without requiring a voltage generator. The proposed SRAM design improves the read performance and energy by 38.6% and 24.9%, respectively.