A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

• Published in: IEEE journal of solid-state circuits Vol. 55; no. 12; pp. 3248 - 3259
• Main Authors: Tang, Xiyuan, Yang, Xiangxing, Zhao, Wenda, Hsu, Chen-Kai, Liu, Jiaxin, Shen, Linxiao, Mukherjee, Abhishek, Shi, Wei, Li, Shaolan, Pan, David Z., Sun, Nan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Analog to digital conversion; Analog to digital converters; analog-to-digital converter (ADC); and temperature (PVT)-robust; Calibration; Capacitors; closed-loop; CMOS; dynamic amplifier; Energy conversion efficiency; Gain; Noise; noise shaping (NS); Power demand; process; Reservoirs; Robustness; successive approximation register (SAR); Sun; Transfer functions; voltage; δσ modulator
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3020194

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only 107 μW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.