A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

• Published in: IEEE journal of solid-state circuits Vol. 53; no. 4; pp. 1227 - 1237
• Main Authors: Ozkaya, Ilter, Cevrero, Alessandro, Francese, Pier Andrea, Menolfi, Christian, Morf, Thomas, Brandli, Matthias, Kuchta, Daniel M., Kull, Lukas, Baks, Christian W., Proesel, Jonathan E., Kossel, Marcel, Luu, Danny, Lee, Benjamin G., Doany, Fuad E., Meghelli, Mounir, Leblebici, Yusuf, Toifl, Thomas
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Circuit design; Clock and data recovery (CDR); Clocks; CMOS; Data recovery; decision feedback equalization (DFE); Decision feedback equalizers; Delays; I/O link; Integrated circuit modeling; Jitter; Laser applications; non-return to zero (NRZ); optical receiver (RX); Optical receivers; phase rotator (PR); self-timed comparator; sensitivity; shunt feedback; Transfer functions; transimpedance amplifier (TIA); variable gain amplifier (VGA); Vibration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2017.2778286

This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock of 15 GHz at 60-Gb/s sampling speed to minimize the CDR loop latency. The RX is characterized in a vertical cavity surface emitting laser-based link recovering a 7-bit pseudo-random bit sequence bit pattern at 60 Gb/s with a JTOL corner frequency of around 80 MHz while maintaining an energy efficiency of 1.9 pJ/bit.