A Low-Noise High-Dynamic-Range 17-b 1.3-Megapixel 30-fps CMOS Image Sensor With Column-Parallel Two-Stage Folding-Integration/Cyclic ADC

• Published in: IEEE transactions on electron devices Vol. 59; no. 12; pp. 3396 - 3400
• Main Authors: Min-Woong Seo, Sawamoto, T., Akahori, T., Zheng Liu, Iida, T., Takasawa, T., Kosugi, T., Watanabe, T., Isobe, K., Kawahito, S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2012; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Capacitors; Circuit properties; CMOS image sensor (CIS); CMOS image sensors; column-parallel folding-integration/cyclic analog-to-digital (A/D) converter (ADC); digital correlated double sampling (CDS); Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Gain; Gray-scale; high dynamic range (DR); Imaging devices; low vertical fixed pattern noise (FPN) (vFPN); multiple sampling technique; Neural networks; Noise measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Solid state circuits; High resolution; Prototype; multiple sampling technique; CMOS image sensors; Digital converter; Implementation; Low voltage; AD converter; digital correlated double sampling (CDS); low vertical fixed pattern noise (FPN) (vFPN); column-parallel folding-integration/cyclic analog-to-digital (A/D) converter (ADC); Sampling; Root mean square value; Multistage circuit; Dynamic response; High performance; Multistage method; high dynamic range (DR); Low noise circuit; AD conversion; Differential circuit; Signalling; Cadmium sulfide; Quantization noise; Gray scale; CMOS image sensor (CIS); Image sensor; Gain
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2012.2215871

A 1.3-megapixel CMOS image sensor (CIS) with digital correlated double sampling and 17-b column-parallel two-stage folding-integration/cyclic analog-to-digital converters (ADCs) is developed. The image sensor has 0.021-e rms - vertical fixed pattern noise, 1.2-e rms - pixel temporal noise, and 85.0-dB dynamic range using 32 samplings in the folding-integration ADC mode. Despite the large number of samplings (32 times), the prototype image sensor is demonstrated at the video rate operation of 30 Hz by the new architecture of the proposed ADCs and the high-performance peripheral logic (or digital) parts using low-voltage differential signaling circuit. The developed 17-b CIS has no visible quantization noise at very low light level of 0.01 lx because of high grayscale resolution where 1LSB = 0.1 - . The implemented CIS using 0.18- μm technology has the sensitivity of 20 V/lx ·s and the pixel conversion gain of 82 μV/e - .