An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 39; no. 12; pp. 4999 - 5010
• Main Authors: Shi, Xiao, Yan, Hao, Wang, Jinxin, Zhang, Jiajia, Shi, Longxing, He, Lei
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive algorithms; Adaptive importance sampling (AIS); Adaptive sampling; Analog circuits; Artificial intelligence; Charge pumps; Computational modeling; Convergence; Estimation; Failure analysis; failure probability; failure regions; Importance sampling; Integrated circuit modeling; Methods; Metropolis–Hastings (MH); Monte Carlo methods; Monte Carlo simulation; Probability; process variation; Resampling; Sampling methods
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.2966481

Performance failure has become a major threat for various memory and analog circuits. It is challenging to estimate the extremely small failure probability when failed samples are distributed in multiple disjoint regions. In this article, we propose an adaptive importance sampling (AIS) algorithm. AIS has several iterations of sampling region adjustments, while existing methods predecide a static sampling distribution. We design two adaptive frameworks based on resampling and population Metropolis-Hastings (MH) to iteratively search for failure regions. The experimental results of the AIS method exhibit better efficiency and higher accuracy. For SRAM bit cell with single failure region, the AIS method uses 2-<inline-formula> <tex-math notation="LaTeX">27{\times } </tex-math></inline-formula> fewer samples and reaches better accuracy when compared to several recent methods. For a two-stage amplifier circuit with multiple failure regions, the AIS method is <inline-formula> <tex-math notation="LaTeX">90{\times } </tex-math></inline-formula> faster than Monte Carlo and 7-23 <inline-formula> <tex-math notation="LaTeX">{\times } </tex-math></inline-formula> over other methods. For charge pump circuit and <inline-formula> <tex-math notation="LaTeX">C^{2}MOS </tex-math></inline-formula> master-slave latch circuit, the AIS method can reach 6-<inline-formula> <tex-math notation="LaTeX">18{\times } </tex-math></inline-formula> and 4-<inline-formula> <tex-math notation="LaTeX">6{\times } </tex-math></inline-formula> speedup over other methods, respectively.