21 fJ/step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

• Published in: IEEE solid-state circuits letters Vol. 3; pp. 342 - 345
• Main Authors: Chandrasekaran, Sanjeev Tannirkulam, Pietri, Stefano, Sanyal, Arindam
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; Analog to digital converters; Analog-to-digital converter (ADC); band-pass (BP) delta–sigma (DS); Band-pass filters; Bandwidth; Bandwidths; CMOS; Energy conversion efficiency; Frequency measurement; Integrators; Mixers; Oscillators; Power consumption; Power demand; Resonant frequency; time interleaved (TI); voltage-controlled oscillator (VCO); Voltage-controlled oscillators
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2020.3019784

A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this letter. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of the signal band and also have intrinsic interferer rejection capability. A prototype ADC fabricated in 65-nm CMOS is operated at an IF of 52 MHz. The ADC has SNDR of 63.1 and 59.5 dB at 1.04 and 4.3-MHz bandwidth, respectively. The ADC consumes only 0.36-mW power from a 0.9-V supply and has an energy efficiency of 21 fJ/step improving upon the current state of the art by <inline-formula> <tex-math notation="LaTeX">3.5\times </tex-math></inline-formula>.