21 fJ/step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC
A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this letter. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture e...
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Published in | IEEE solid-state circuits letters Vol. 3; pp. 342 - 345 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Piscataway
IEEE
2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this letter. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of the signal band and also have intrinsic interferer rejection capability. A prototype ADC fabricated in 65-nm CMOS is operated at an IF of 52 MHz. The ADC has SNDR of 63.1 and 59.5 dB at 1.04 and 4.3-MHz bandwidth, respectively. The ADC consumes only 0.36-mW power from a 0.9-V supply and has an energy efficiency of 21 fJ/step improving upon the current state of the art by <inline-formula> <tex-math notation="LaTeX">3.5\times </tex-math></inline-formula>. |
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ISSN: | 2573-9603 2573-9603 |
DOI: | 10.1109/LSSC.2020.3019784 |