Design of a Refresh-Controller for GC-eDRAM Based FIFOs

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 12; pp. 4804 - 4817
• Main Authors: Noy, Tzachi, Teman, Adam
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Capacitors; Control systems design; Dynamic random access memory; embedded dynamic random access memory (eDRAM); First-in first-out (FIFO); gain-cells (GCs); Integrated circuits; low power; memory availability; Memory management; Power consumption; Random access memory; retention time; Static random access memory; System-on-chip
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.2998582

First-in first-out (FIFO) queues are ubiquitous building blocks in modern system-on-chips. Big FIFOs are often realized as static random access memories (SRAMs), and in many cases account for a significant portion of the area and power consumption of integrated circuits (ICs). Gain-cell embedded DRAM (GC-eDRAM) technology is an embedded memory alternative to the pervasive SRAM technology in ICs. It consumes less silicon area and less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. In this paper we leverage the unique access patterns implied by the FIFO scheme to design a FIFO realized with GC-eDRAM. We show that such a FIFO is functionally indistinguishable from a FIFO realized with SRAM. The proposed FIFO has no access blockage time due to refresh, and no data integrity issues, and so can be used as an out-of-the-box replacement for FIFOs in existing and future designs, while providing as much as a <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula> reduction in both area and power as compared to SRAM.