A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays

• Published in: IEEE journal of solid-state circuits Vol. 56; no. 2; pp. 488 - 500
• Main Authors: Kim, Jong-Seok, Yoon, Jin-O, Choi, Byong-Deok
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Active-matrix display; Amplifiers; Capacitance; Capacitors; CMOS; column driver IC; Decoding; Digital to analog conversion; Digital to analog converters; digital-to-analog converter (DAC); Error analysis; Integrated circuits; Liquid crystal displays; liquid-crystal display (LCD); Logic circuits; low-voltage resistor-string DAC (LVDAC); MOSFET; MOSFETs; Nonlinearity; organic light emitting diode (OLED) display; Organic light emitting diodes; Parasitics (electronics); Switching circuits
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3024704

To reduce the circuit area and support a 10-bit fully nonlinear gamma correction, a new column driver architecture constructed with a 10-bit one-stage low-voltage resistor string digital-to-analog converter (RDAC) (LVDAC) and a switched-capacitor amplifier (SC-AMP) is proposed. Because the LVDAC is implemented with low-voltage (LV) MOSFETs instead of high-voltage (HV) MOSFETs, the circuit area is drastically reduced. In addition, there is no need to use level shifters that must be used in the traditional column driver between the LV logic circuit and the HV DAC, thus further decreasing the circuit area. By utilizing a one-stage DAC architecture, the effective bit resolution of nonlinear gamma correction can be increased compared with previous two-stage DACs, in which the output voltages of the coarse DAC are interpolated. The output voltage of LVDAC is amplified by SC-AMP to reach the requisite HV to drive the display panel. In designing the SC-AMP, the effects of non-idealities, such as random offset voltage, capacitance mismatch, parasitic capacitance, and switching error are quantitatively analyzed, and circuit techniques to suppress the effects are presented. The proposed column driver was fabricated using a 90-nm CMOS process. The circuit area of the proposed 10-bit column driver is only 69.0% of that of the conventional 8-bit column driver because the conventional 8-bit HV RDAC (HVDAC) using 5-V MOSFETs is replaced by the proposed 10-bit LVDAC using 1.2-V MOSFETs, along with the SC-AMP with a gain of four to support the 5-V output voltage range. The measurement results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.2/−0.18 and +0.42/−0.06 LSB, respectively, with an LSB voltage of 4.5 mV. The measured maximum deviation of voltage outputs (DVOs) between 50 channels is 7.9 mV.