Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory

• Published in: IEEE journal of solid-state circuits Vol. 57; no. 4; pp. 986 - 998
• Main Authors: Kim, Sung, Fayazi, Morteza, Daftardar, Alhad, Chen, Kuan-Yu, Tan, Jielun, Pal, Subhankar, Ajayi, Tutu, Xiong, Yan, Mudge, Trevor, Chakrabarti, Chaitali, Blaauw, David, Dreslinski, Ronald, Kim, Hun-Seok
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Algorithms; Bandwidth; data movement; data reuse; energy efficiency; Field programmable gate arrays; Hardware; Heuristic algorithms; Indexes; interconnect; multicore architecture; Multiprocessing; on-chip memory; programmability; Reconfiguration; Synchronism; Synchronization; System-on-chip; systolic arrays
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2022.3140241

We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa's design features culminate in median energy-efficiency improvements of 37.2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> and 11.6<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> over mobile CPU and GPU baselines, respectively.