SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 37; no. 11; pp. 2802 - 2811
• Main Authors: Alan, Tanfer, Henkel, Jorg
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Approximate computing; Approximation; Circuit synthesis; cross-layer design; Delays; Design automation; design space exploration; Electronic design automation; Embedded systems; Frequency synthesizers; Logic synthesis; Methodology; Optimization; Reduction; Resilience; Scaling; Space exploration
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2018.2858364

We present a novel systematic logic synthesis methodology, that assesses potential delay improvements in noncritical paths for any circuit. It synthesizes them with tighter constraints toward minimizing the number of near-critical paths and, as a result, reducing the probability of timing violations when frequency is overscaled. We demonstrate that our methodology reduces the number of near-critical paths by up to 93% and offer favorable accuracy and performance tradeoffs, up to <inline-formula> <tex-math notation="LaTeX">15{\times } </tex-math></inline-formula> reduction in error rate and <inline-formula> <tex-math notation="LaTeX">7{\times } </tex-math></inline-formula> reduction in mean relative error under timing speculations when compared to traditional synthesis methods. Additionally, when used together with precision scaling in cross-layer approximation techniques, it facilitates a further 27% frequency increase over an increase achievable with traditional synthesis methods. The area and power overheads of experimented circuits are up to 14% and 12%, respectively. Our methodology is compatible with traditional Electronic design automation flows. It inherits the rich feature set of existing tools and leverages their entire scope of optimizations.