A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort

This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR function with charge pump, the power efficiency and li...

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Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 66; no. 8; pp. 2907 - 2920
Main Authors Moon, Yong-Hwan, Yoo, Jae-Wook, Ryu, Young-Soo, Kim, Sang-Ho, Son, Kyung-Sub, Kang, Jin-Ku
Format Journal Article
LanguageEnglish
Published New York IEEE 01.08.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
CDR circuits
Charge efficiency
Charge pumps
Clock and data recovery (CDR)
Clocks
CMOS
current controlled oscillator (CCO)
Data recovery
Detectors
Digital electronics
embedded DisplayPort (eDP)
Frequency control
Frequency locked loops
Linear phase
Linearity
Phase detectors
Phase frequency detector
Phase locked loops
Power consumption
Power efficiency
Pulse duration
quarter-rate linear phase detector (QLPD)
Sensors
Vibration
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Summary:This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR function with charge pump, the power efficiency and linearity of the phase detector are improved. The proposed QLPD responds correctly up to 0.75 UI of phase difference at 5.4 Gb/s. The CDR was designed to conform to Embedded DisplayPort (eDP) standard of the Video Electronics Standards Association (VESA). The proposed CDR circuit has been fabricated using a 40-nm CMOS technology. The jitter tolerance (JTOL) margin was measured at 0.75 UI, which is 20% higher than the eDP specification of 0.624 UI at the 20-MHz jitter frequency. BER was measured as less than 10 −12 with a 2 7 −1 pseudo random bit sequence (PRBS) pattern. The CDR consumes 12.99 mW, including a bandgap reference circuit and power efficiency achieving 2.41 pJ/bit at 5.4 Gb/s. The area of the proposed CDR is 0.13 mm 2 .
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2906877