112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels

• Published in: IEEE journal of solid-state circuits Vol. 55; no. 4; pp. 1077 - 1085
• Main Authors: Krupnik, Yoel, Perelman, Yevgeny, Levin, Itamar, Sanhedrai, Yosi, Eitan, Roee, Khairi, Ahmad, Shifman, Yizhak, Landau, Yoni, Virobnik, Udi, Dolev, Noam, Meisler, Alon, Cohen, Ariel
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 112 Gb/s; Analog to digital conversion; Analog to digital converters; analog-to-digital converter (ADC); Bandwidth; Bit error rate; Channels; Clock recovery; Clocks; Data recovery; Decision feedback equalizers; Equalization; Error correction; Ethernet; feed-forward equalizer (FFE); Gain; Impedance; PAM4; Receivers; SAR; serializer/de-serializer transceiver (SERDES)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2959511

A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach, −35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.