A Hardware Architecture for Radial Basis Function Neural Network Classifier

• Published in: IEEE transactions on parallel and distributed systems Vol. 29; no. 3; pp. 481 - 495
• Main Authors: Mohammadi, Mahnaz, Krishna, Akhil, S., Nalesh, Nandy, S.K.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Basis functions; Classification; Cluster analysis; Clustering; Clustering algorithms; Computer architecture; Copper; Data classification; Datasets; Hardware; Kernel; Neural networks; parallel and pipelined architectures; Radial basis function; RBFNN classifier; reconfigurable computing; scalable architectures; Training; Vector quantization; Weight
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/TPDS.2017.2768366

In this paper we present design and analysis of scalable hardware architectures for training learning parameters of RBFNN to classify large data sets. We design scalable hardware architectures for K-means clustering algorithm to training the position of hidden nodes at hidden layer of RBFNN and pseudoinverse algorithm for weight adjustments at output layer. These scalable parallel pipelined architectures are capable of implementing data sets with no restriction on their dimensions. This paper also presents a flexible and scalable hardware accelerator for realization of classification using RBFNN, which puts no limitation on the dimension of the input data is developed. We report FPGA synthesis results of our implementations. We compare results of our hardware accelerator with CPU, GPU and implementations of the same algorithms and with other existing algorithms. Analysis of these results show that scalability of our hardware architecture makes it favorable solution for classification of very large data sets.