Design of a K-Band High-Linearity Asymmetric SPDT CMOS Switch Using a Stacked Transistor

This study presents a high-linearity K - band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using...

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Bibliographic Details
Published inIEEE microwave and wireless components letters Vol. 32; no. 12; pp. 1443 - 1446
Main Authors Kim, Taehun, Lee, Hui Dong, Park, Bonghyuk, Jang, Seunghyun, Kong, Sunwoo, Park, Changkun
Format Journal Article
LanguageEnglish
Published IEEE 01.12.2022
Subjects
CMOS
high linearity
Insertion loss
K-band
Logic gates
Loss measurement
millimeter-wave (mm-wave)
Semiconductor device measurement
single-pole double-throw (SPDT)
switch
Switches
Switching circuits
Transistors
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Summary:This study presents a high-linearity K - band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20-25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP1 dB) are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm2.
ISSN:1531-1309
1558-1764
DOI:10.1109/LMWC.2022.3192440