65.6-75.2-GHz Phase-Controlled Push-Push Frequency Quadrupler With 8.3% DC-to-RF Efficiency in 40-nm CMOS

We present a 40-nm CMOS 70-GHz frequency quadrupler based on a phase-controlled push-push (PCPP) topology that provides high efficiency and harmonic suppression. Since MOSFETs in the PCPP stack turn off alternately, the quadrupler can provide high energy efficiency even for fourth-order frequency mu...

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Bibliographic Details
Published inIEEE microwave and wireless components letters Vol. 31; no. 6; pp. 579 - 582
Main Authors Lee, Kangseop, Kim, Kyunghwan, Shin, Gibeom, Song, Ho-Jin
Format Journal Article
LanguageEnglish
Published IEEE 01.06.2021
Subjects
CMOS
Energy efficiency
frequency multiplier
frequency quadrupler
Harmonic analysis
millimeter-wave integrated circuit
phase-controlled push–push
Power amplifiers
Power generation
Power harmonic filters
Topology
Wireless communication
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Summary:We present a 40-nm CMOS 70-GHz frequency quadrupler based on a phase-controlled push-push (PCPP) topology that provides high efficiency and harmonic suppression. Since MOSFETs in the PCPP stack turn off alternately, the quadrupler can provide high energy efficiency even for fourth-order frequency multiplication. One major problem related to even-order harmonic suppression was mitigated by using a transformer-based output amplifier with no degradation in energy efficiency. The fabricated quadrupler provides the 3-dB bandwidth and peak output power of 65.6-75.2 GHz and −0.2 dBm at 70 GHz, respectively, with an 8.9-dBm fundamental input power. The peak dc-to-RF efficiency was measured to be 8.3% with 11.4-mW dc power consumption, including an output amplifier. At 70 GHz, measured harmonic suppression was around 51.1, 41.0, and 43.1 dBc at first, second, and third harmonic frequencies, respectively.
ISSN:1531-1309
1558-1764
DOI:10.1109/LMWC.2021.3068179