A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR

• Published in: IEEE journal of solid-state circuits Vol. 52; no. 12; pp. 3262 - 3275
• Main Authors: Duncan, Lucas, Dupaix, Brian, McCue, Jamin J., Mathieu, Brandon, LaRue, Matthew, Patel, Vipul J., Teshome, Mesfin, Myung-Jun Choe, Khalil, Waleed
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Calibration; Current-steering (CS); DC-AC power converters; Digital to analog conversion; Digital to analog converters; digital-to-analog converter (DAC); direct digital-to-RF; Frequency response; high linearity; high speed; Intermodulation distortion; Linearity; multiple Nyquist; return-to-zero (RZ); RF-DAC; Silicon germanides; Silicon germanium; Switches; Timing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2017.2749441

A dc-20-GHz multiple-return-to-zero digital-to-analog converter (DAC) is proposed for direct radio frequency synthesis. To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed. While the VST minimizes variation in frequency response among the MSB cells, the FF path improves matching between the MSBs and LSBs, providing up to 21-dB improvement in simulated spurious-free dynamic range (SFDR) at 20 GHz. To account for additional errors introduced by process variation, the DAC utilizes per-cell calibration of both amplitude and timing. The DAC is implemented in a 0.13-μm SiGe process with an area of 6.25 mm 2 and consumes 1.91 W. After amplitude and timing calibration, >48-dB SFDR and lesser than -46 dBc intermodulation distortion are achieved from dc to 20 GHz.