A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 54; no. 3; pp. 821 - 833
• Main Authors: Kexu Sun, Guanhua Wang, Qing Zhang, Elahmadi, Salam, Ping Gui
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive optics; Analog to digital conversion; Analog to digital converters; Analog-to-digital converter (ADC); Buffers; calibration; Clocks; CMOS; coherent receiver; fiber optic communication; Optical distortion; Optical polarization; Optical receivers; SAR; Signal to noise ratio; time interleaved (TI)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2884352

This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to 17.5 and 27.1 GHz, respectively. To achieve the ENOB requirement over the entire Nyquist BW in 100-/200-Gb/s digital coherent receivers, several ENOB and BW enhancement techniques are presented. First, a low-noise parametric T/H amplifier is proposed to amplify the sampled signal and improve the SNR of the subsequent sub-channel ADCs. Second, a switched sub-channel buffer is proposed to avoid the distortion caused by the limited BW of the sub-channel buffer during tracking. Finally, multiple BW enhancing techniques are employed. The entire chip is fabricated in the 28-nm CMOS process, occupies an active area of 0.878 mm 2 , and consumes 702 mW.