A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization

Learning vector quantization (LVQ) neural networks have already been successfully applied for image compression and object recognition. In this paper, we propose a modular and reconfigurable pipeline architecture (MRPA) for LVQ. The MRPA consists of dynamically reconfigurable modules and realizes a...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 65; no. 10; pp. 3312 - 3325
Main Authors Zhang, Xiangyu, An, Fengwei, Chen, Lei, Ishii, Idaku, Mattausch, Hans Jurgen
Format Journal Article
LanguageEnglish
Published New York IEEE 01.10.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:Learning vector quantization (LVQ) neural networks have already been successfully applied for image compression and object recognition. In this paper, we propose a modular and reconfigurable pipeline architecture (MRPA) for LVQ. The MRPA consists of dynamically reconfigurable modules and realizes a run-time and on-chip configuration for recognition and learning. Prototype fabrication in 65-nm CMOS technology verifies high integration density and memory-utilization efficiency, good performance, and considerable flexibility in vector dimensionality, number of weight-vectors, and adaption strategies. Compared with the embedded microprocessors, which rely on single-instruction-multiple-data processing, the developed prototype increases the performance of both recognition and learning operations. The MRPA prototype shows improvements by factors of approximately 40 and 101 on the well-established performance metrics million connections per second for recognition and million connection updates per second for learning, respectively.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2018.2804946