Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

• Published in: IEEE transactions on electron devices Vol. 60; no. 10; pp. 3500 - 3507
• Main Authors: Altolaguirre, Federico Agustin, Ming-Dou Ker
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Clamps; CMOS process; Design. Technologies. Operation analysis. Testing; Dielectric, amorphous and glass solid devices; Diodes; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Electrostatic discharge (ESD); Electrostatic discharges; Exact sciences and technology; gate leakage; Integrated circuits; Leakage currents; power-rail clamp circuit; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; silicon controlled rectifier (SCR); Temperature measurement; Thyristors; Gate current; Diode; Power circuit; Electrostatic discharge; Transistor; Power electronics; power-rail clamp circuit; Controlled rectifier; Implementation; MOS capacitor; Low voltage; Trigger; Silicon rectifier; Complementary MOS technology; silicon controlled rectifier (SCR); gate leakage; Electrostatic discharge (ESD); Leakage current; Silicon
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2013.2274701

A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the power-rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design.