A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 68; no. 8; pp. 3242 - 3253
• Main Authors: Lim, Chaegang, Choi, Yohan, Park, Yunsoo, Song, Jaegeun, Ahn, Soon-Sung, Park, Sooho, Kim, Chulwoo
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 1/<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">f noise; analog-to-digital converter (ADC); Bandwidth; Capacitors; CCIA; Choppers (circuits); chopping artifacts; chopping technique; CMOS; CTΔΣM; Cutting; Gain; Harmonic distortion; Integrated circuits; Linearity; Modulation; noise-folding; Oversampling; Quantization (signal); Rejection; ripple; Ripples; RRL; sensor readout IC; spike
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2021.3084350

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> modulator (CT<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and <inline-formula> <tex-math notation="LaTeX">1/f </tex-math></inline-formula> noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (<inline-formula> <tex-math notation="LaTeX">f_{ch} </tex-math></inline-formula>) same as the sampling frequency (<inline-formula> <tex-math notation="LaTeX">f_{s} </tex-math></inline-formula>). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm 2 , drawing <inline-formula> <tex-math notation="LaTeX">232.2~\mu \text{A} </tex-math></inline-formula> at a 1.8 V supply. The proposed capacitively coupled (CC)-CT<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula> has a 19.4 nV/<inline-formula> <tex-math notation="LaTeX">\sqrt {Hz} </tex-math></inline-formula> input-referred noise density, <inline-formula> <tex-math notation="LaTeX">1.9~\mu \text{V} </tex-math></inline-formula> offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV<inline-formula> <tex-math notation="LaTeX">_{pp} </tex-math></inline-formula>. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.