A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 68; no. 8; pp. 3305 - 3316
• Main Authors: Lee, Eunyoung, Han, Taeyoung, Seo, Donguk, Shin, Gicheol, Kim, Jaerok, Kim, Seonho, Jeong, Soyoun, Rhe, Johnny, Park, Jaehyun, Ko, Jong Hwan, Lee, Yoonmyung
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Artificial neural networks; bit-scalable; Capacitors; charge-domain compute; Computation; Computer architecture; Couplings; deep neural networks; Domains; Energy efficiency; In-memory computing; machine learning; Merging; Microprocessors; Neural networks; SRAM cells; Static random access memory; Sums; Transistors; Weight
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2021.3080042

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8-b weight to 119.2 TOPS/W for 2-b weight.