Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 64; no. 12; pp. 3126 - 3137
• Main Authors: Silveira, Bianca, Paim, Guilherme, Abreu, Brunno, Grellert, Mateus, Diniz, Claudio Machado, da Costa, Eduardo Antonio Cesar, Bampi, Sergio
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: adder compressors; CMOS; Coders; Coding standards; Compressors; Computer architecture; Encoding; Energy efficiency; Hardware; HEVC; low power; Low power electronics; Motion estimation; Motion simulation; real-time encoding; SAD; State of the art; Synthesis; Video coding; Video compression; VLSI architecture
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2017.2728802

Sum of absolute differences (SAD) calculation is one of the most time-consuming operations of video encoders compatible with the high efficiency video coding standard. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper exploits different adder compressors structures into the SAD hardware architecture. The architectures were synthesized to 45-nm CMOS standard cells. Synthesis results show that SAD architecture using 8-2 compressor composed with 4-2 compressors and Kogge-Stone adder in the recombination line reduces power dissipation by 25.5% on average when compared with the SAD architecture using conventional adders from a state-of-the-art synthesis tool. Our throughput analysis shows that the designed SAD units are capable of encoding full HD (1920×1080) videos in real time at 30 frames/s.