Investigation of poly silicon channel variation in Vertical 3D NAND flash memory

• Published in: IEEE access Vol. 10; p. 1
• Main Authors: Lee, Inyoung, Kim, Dae Hwan, Kang, Daewoong, Cho, Il Hwan
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3D NAND; Curvature; Electric fields; electron back tunneling; Electron traps; Flash memory (computers); Logic gates; Mathematical analysis; poly-Si channel; Polysilicon; Surface waves; Three-dimensional displays; Tunneling; wave-shaped channel
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2022.3212540

Since the most of three dimensional (3D) NAND devices' channel is composed of polysilicon grain, the actual 3D NAND channel has a wave-shaped channel, not uniform shape. In this study, we defined the curvature of the channel as a 'Wave Factor (WF)' parameter, and simulated 3D NAND device with the WF applied channel. Various effects of the curvature in the channel on the program and erase operation of the device have been investigated. When the channel is wave-shaped, the electric field tends to be concentrated on the corner region of the blocking oxide during the program operation, which causes increase of the electron back tunneling to the gate. Therefore, program speed degraded as the WF value higher. During the erase operation, the same with program operation, the electric field concentrated on the corner of the blocking oxide increased, enhanced electron back tunneling from the metal gate occurred while less amount of hole charge trapped. As a result, VTH shift after the erase operation decreased according to increased WF. This phenomenon becomes more serious on the short channel condition. In addition, the result shows that degradation of erase characteristic by WF can be prevented by applying thicker blocking oxide.