A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 49; no. 3; pp. 673 - 682
• Main Authors: Danjo, Takumi, Yoshioka, Masato, Isogai, Masayuki, Hoshino, Masanori, Tsukamoto, Sanroku
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-digital conversion; Calibration; Capacitance; CMOS analog integrated circuits; CMOS integrated circuits; Control systems; foreground calibration; Interpolation; subranging; Threshold voltage; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2297416

A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the analog signals, thereby eliminating the errors between the coarse and fine decisions that occur when two different samplers are used to capture the signal. Both decisions use the same comparators, and a digitally assisted calibration circuit compensates for the errors in the different threshold levels used for the two decisions. This calibration eliminates redundant comparators, and thus, reduces the area. Reference voltages generators, which are implemented using resistor ladders in conventional subranging ADCs, are eliminated thanks to the use of the CDACs together with interpolation in the comparators. This solves two problems related to the resistor ladder, namely, the trade-off between the settling time and the static-current consumption and signal dependent on-resistance of switches connected to intermediate potential nodes. A test chip fabricated in 65-nm CMOS technology operates at 1 GS/s with SNDR of 32.8 dB. Its active area is 0.044 mm 2 , and its power consumption is 9.9 mW at a 1.1-V supply voltage.