UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision

• Published in: IEEE journal of solid-state circuits Vol. 54; no. 1; pp. 173 - 185
• Main Authors: Lee, Jinmook, Kim, Changhyeon, Kang, Sanghoon, Shin, Dongjoo, Kim, Sangyeob, Yoo, Hoi-Jun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Artificial neural networks; Biological neural networks; Bit serial; CMOS; deep learning; deep learning ASIC; deep learning hardware; deep neural network (DNN); Electric potential; Energy consumption; Energy efficiency; Hardware; Lookup tables; Machine learning; Mathematical model; mobile deep learning; Neural networks; Power efficiency; Table lookup; Weight
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2865489

An energy-efficient deep neural network (DNN) accelerator, unified neural processing unit (UNPU), is proposed for mobile deep learning applications. The UNPU can support both convolutional layers (CLs) and recurrent or fully connected layers (FCLs) to support versatile workload combinations to accelerate various mobile deep learning applications. In addition, the UNPU is the first DNN accelerator ASIC that can support fully variable weight bit precision from 1 to 16 bit. It enables the UNPU to operate on the accuracy-energy optimal point. Moreover, the lookup table (LUT)-based bit-serial processing element (LBPE) in the UNPU achieves the energy consumption reduction compared to the conventional fixed-point multiply-and-accumulate (MAC) array by 23.1%, 27.2%, 41%, and 53.6% for the 16-, 8-, 4-, and 1-bit weight precision, respectively. Besides the energy efficiency improvement, the unified DNN core architecture of the UNPU improves the peak performance for CL by 1.15<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> compared to the previous work. It makes the UNPU operate on the lower voltage and frequency for the given DNN to increase energy efficiency. The UNPU is implemented in 65-nm CMOS technology and occupies the <inline-formula> <tex-math notation="LaTeX">4 \times 4 </tex-math></inline-formula> mm 2 die area. The UNPU can operates from 0.63- to 1.1-V supply voltage with maximum frequency of 200 MHz. The UNPU has peak performance of 345.6 GOPS for 16-bit weight precision and 7372 GOPS for 1-bit weight precision. The wide operating range of UNPU makes the UNPU achieve the power efficiency of 3.08 TOPS/W for 16-bit weight precision and 50.6 TOPS/W for 1-bit weight precision. The functionality of the UNPU is successfully demonstrated on the verification system using ImageNet deep CNN (VGG-16).